1. Technical Field of the Invention
The present invention relates generally to semiconductor memories, and more particularly, to a memory array where memory cells can be reset without a write cycle following a read cycle.
2. Description of Related Art
It is well known that memory performance and usage is a key component in optimizing electronic systems that require memory. Such systems often demand efficient use of memory by minimizing access time, reducing the number of memory cycles (i.e., read/write cycles) and/or power consumption, etc. These factors become more significant where expensive memory with special functionality is required for certain system-level applications such as telecommunications equipment (e.g., routers having network processors), address translators for Asynchronous Transfer Mode (ATM) address mapping, table look-up and mapping applications, et cetera. In order to improve the system performance and save silicon area in such applications, it is incumbent upon hardware designers to strive for solutions that reduce memory cycles.
Content Addressable Memory (CAM) is a specialized memory that is widely used in network equipment applications. CAM cells are memory cells that are addressed in response to their content, rather than by a physical address within the array. Once the CAM array is initialized with data entries, the entire CAM can be searched in a single operation. To determine if a data value is still stored in the CAM array, a compare operation is performed by the CAM cells. To better manage the CAM usage, results of the compare operation are typically used in conjunction with another associative memory that is periodically read for determining CAM usage. As part of its monitoring function, the associative memory is required to be reset to zero in order to be able to detect if one or more corresponding CAM cells are available for new data entry.
Those skilled in the art should appreciate that resetting the associative memory (or any random access memory, for that matter) typically involves effectuating write cycles for storing binary 0""s in selected cell locations and such write cycles expend time that might be otherwise used more beneficially. Further, reducing or eliminating the write cycles also optimizes the overall performance of a system, for example, the CAM memory usage management exemplified hereinabove.
Accordingly, the present invention advantageously provides circuitry and associated method for resetting a memory storage cell without a dedicated write cycle therefor. Preferably, the storage cell is provided as part of an age_array employed for monitoring the usage of a Content Addressable Memory (CAM). When a match between search data and contents of a particular location of the CAM is found, a Match signal is generated to set a memory storage cell of the age_array (referred to as an age_cell) corresponding to the particular CAM location. When the age_array is read, the wordline (WL) associated with the age_cell is driven high. Upon developing a voltage separation between the data and data bar nodes of the age_cell, a sense amp senses the data value on the corresponding bit (BT) and bit bar (BB) lines coupled thereto. A suitable data out signal is generated for outputting the sensed data. A control signal (hereinafter referred to as reset control signal) is generated to indicate that the data sense operation is substantially complete with respect to that age_cell. The reset control signal is applied during the read cycle to the age_cell to drive the data node thereof to ground in order to store a binary 0 thereat. Furthermore, the control signal is also provided to the age_array control block in order to deactivate the selected WL. Accordingly, the need for dedicated write cycles to reset the age_array for further monitoring of the CAM usage after the read cycles is advantageously obviated.
In a presently preferred exemplary embodiment, the reset circuitry provided with the age_cells comprises two NMOS transistors wherein one transistor (data discharge transistor) is coupled to the data node of the age_cell and the other transistor (pull-down transistor) is coupled thereto and ground. The reset control signal is applied to the gate of the pull-down transistor and the selected WL is applied to the gate of the data discharge transistor.
In a further aspect, the present invention is directed to semiconductor memory circuit which comprises a plurality of storage cells, each having a data node and a data bar node; and circuitry coupled to at least one storage cell for discharging the data node associated therewith during a read cycle with respect to the storage cell being accessed.
In yet further aspect, the present invention is directed to a memory system which comprises a CAM block including a plurality of locations operable to store a plurality of contents and an age_array operably associated with the CAM block for monitoring the plurality of locations to determine whether a particular location of the CAM block is available for storing new content data thereat. The age_array preferably comprises a plurality of age_cells organized as an N-by-1 array, wherein each age_cell corresponds to a specific location in the CAM block. An age_cell is set to a binary one when a match is found between the contents of a select location of the CAM block corresponding to the age_cell and an externally supplied search data. The memory system also includes reset circuitry provided with each age_cell to clear the age_cell during a read operation with respect to the age_cell. Preferably, the reset circuitry is operable in response to a reset control signal generated to indicate that the read operation is substantially complete.